1. Field of the Invention
The present invention generally relates to a semiconductor memory device, and particularly to a dynamic semiconductor memory device with information stored in a capacitor. More particularly, the present invention relates to a dynamic semiconductor memory device suitable for integration into a system LSI large scale integrated circuit) and operating under a low power supply voltage.
2. Description of the Background Art
A dynamic random access memory (DRAM) is generally used in order to implement a mass storage memory in a system LSI with a memory and a logic integrated therein. The DRAM includes memory cells each formed of a single capacitor and a single transistor, and therefore, the memory cell occupies a small area. Moreover, the cost per bit is inexpensive. As a result, the DRAM can implement a mass storage memory with a small occupying area.
FIG. 27 is a diagram schematically showing the structure of a main part of a conventional DRAM. FIG. 27 shows memory cells MC0 and MC1 arranged in two rows and one column in a memory cell array. Bit lines BL and /BL are provided for the memory cell column, and a word line WL (WL0, WL1) are provided for each memory cell row. In FIG. 27, memory cell MC0 is located at an intersection of bit line BL and word line WL0, whereas memory cell MC1 is located at an intersection of bit line /BL and word line WL1.
Each of memory cells MC0, MC1 includes a capacitor Cs for storing information, and an accessing MOS transistor (insulated-gate field effect transistor) MT. Each access transistor MT is connected through a capacitor contact to an associated memory cell capacitor Cs, and also connected through a bit line contact to a corresponding bit line BL or /BL. An electrode node of each capacitor Cs connected to the capacitor contact is referred to as a storage node SN (SN0, SN1). Charges according to the stored data are accumulated in storage node SN. A cell-plate voltage Vcp (=Vccs/2) is applied to the other electrode node (cell-plate electrode node) of each memory cell capacitor Cs.
Memory cells MC0 and MC1 store information by charges accumulated in the respective storage nodes SN0 and SN1. Usually, word lines WL0 and WL1 receive a high voltage Vpp of about 3.6 V, higher than a sense power supply voltage, when selected. Such high voltage Vpp is applied in order to write high-level data of a sufficiently high voltage level (sense power supply voltage) to storage nodes SN0 and SN1 without a threshold-voltage loss across the corresponding access transistors MT. Bit lines BL and /BL have a voltage amplitude of about 2.0 V (=Vccs). The state in which data at a voltage Vccs level is stored in storage node SN0 or SN1 is referred to as high-level data storage, whereas the state in which data at a ground-voltage GND level is stored in storage node SN0 or SN1 is referred to as low-level data storage.
A circuit for reading the data stored in memory cell MC0 or MC1 is called a sense amplifier circuit. The sense amplifier circuit includes a sense amplifier 900 that is activated to differentially amplify a voltage on bit lines BL and /BL, and sense activation transistors PQ3 and NQ3 responsive to respective sense amplifier activation signals /SOP and SON for transmitting a power supply voltage Vccs and ground voltage GND to internal power source nodes of sense amplifier 900, respectively. Sense amplifier 900 includes a P-channel MOS transistor PQ1 connected between a first internal power source node and bit line BL and having its gate connected to bit line /BL, a P-channel MOS transistor PQ2 connected between the first internal power source node and bit line /BL and having its gate connected to bit line BL, an N-channel MOS transistor NQ1 connected between bit line BL and a second internal power source node and having its gate connected to bit line /BL, and an N-channel MOS transistor NQ2 connected between bit line /BL and the second internal power source node and having its gate connected to bit line BL. Sense amplifier activation transistor PQ3 formed by a P-channel MOS transistor is rendered conductive in response to activation of sense amplifier activation signal /SOP for transmitting sense power supply voltage Vccs to the first internal power source node. Sense amplifier activation transistor NQ3 formed by an N-channel MOS transistor is rendered conductive in response to activation of sense amplifier activation signal SON for transmitting ground voltage GND to the second internal power source node.
A bit-line precharging/equalizing circuit 902 is further provided in order to precharge and equalize bit lines BL and /BL to an intermediate voltage in the standby state. Bit-line precharging/equalizing circuit 902 includes N-channel MOS transistors NQ4 and NQ5 rendered conductive in response to activation of a bit-line equalization instruction signal BLEQ for transmitting a bit-line precharge voltage VBL (=Vccs/2) to bit lines BL and /BL, and an N-channel MOS transistor NQ6 rendered conductive in response to activation of bit-line equalization instruction signal BLEQ for electrically short-circuiting bit lines BL and /BL.
Bit-line precharging/equalizing circuit 902 is used to precharge and equalize bit lines BL and /BL to the intermediate voltage level during the standby state. As a result, bit lines BL and /BL have a reduced amplitude in sensing operation, whereby high-speed sensing as well as reduction in a sense current are achieved. Now, the operation of reading the data in the memory cells shown in FIG. 27 is briefly described with reference to FIGS. 28 and 29.
Referring first to FIG. 28, a sensing operation for reading high-level data (H data) stored in storage node SN0 of memory cell MC0 is described. In the standby state, bit lines BL and /BL are precharged and equalized to the intermediate voltage Vccs/2 level by bit-line precharging/equalizing circuit 902. Sense amplifier activation signal /SOP is at the sense power supply voltage Vccs level, whereas sense amplifier activation signal SON is at the ground voltage GND level. Accordingly, sense amplifier activation transistors PQ3 and NQ3 are both in the OFF state.
When an active cycle is started, bit-line equalization instruction signal BLEQ first becomes inactive, whereby bit-line precharging/equalizing circuit 902 is deactivated. Thus, bit lines BL and /BL are brought into a floating state at the intermediate voltage Vccs/2 level.
Then, a row selecting operation is performed according to an address signal not shown, and word line WL0 is selected. The selected word line WL0 is driven to the high voltage Vpp level that is higher than sense power supply voltage Vccs. Access transistor MT of memory cell MC0 is rendered conductive in response to the voltage rise on word line WL0. As a result, storage node SN0 is coupled to bit line BL, and charges accumulated in storage node SN0 are transmitted onto bit line BL. Since H data (high level data) is stored in storage node SN0, bit line BL voltage is raised by a reading voltage xcex94V from precharge voltage Vccs/2 (the voltage levels on bit line BL and storage node SN0 become equal to each other). However, since there is no memory cell arranged at the intersection of bit line /BL and word line WL0, bit line /BL is maintained at the precharge-voltage Vccs/2 level.
When the voltage difference between bit lines BL and /BL, i.e., the reading voltage xcex94V, is sufficiently developed, sense amplifier activation signals SON and /SOP are activated. As a result, sense amplifier activation transistors PQ3 and NQ3 are rendered conductive, and sense amplifier 900 starts the sensing operation. During the sensing operation, sense amplifier 900 differentially amplifies the read voltage xcex94V on bit lines BL and /BL, thereby driving bit line BL to the sense power supply voltage Vccs level and bit line /BL to the ground voltage level.
Referring now to FIG. 29, a sensing operation for reading low-level data (L data) stored in storage node SN0 of memory cell MC0 is described.
This L-data sensing operation is the same as the H-data sensing operation of FIG. 28 until word line WL0 is driven to the high voltage Vpp level. In the case where the L data is stored in storage node SN0, bit line BL voltage lowers from the intermediate voltage, whereby the voltage levels on storage node SN0 and bit line BL finally become equal to each other. Then, sense amplifier activation signals SON and /SOP are activated. As a result, sense amplifier 900 operates to drive bit line BL to the ground voltage level (L level) and bit line /BL to the sense power supply voltage Vccs level.
In the H-data read operation, bit line BL attains a voltage V(HBL) as given by the following expression:
V(HBL)=(1+1/(1+Cb/Cs))xc2x7Vccs/2 
, where Cb indicates parasitic capacitance of bit line BL, and Cs indicates a capacitance value of memory cell capacitor Cs. In the L-data read operation, bit line BL attains a voltage V(LBL) as given by the following expression:
V(LBL)=(1xe2x88x921/(1+Cb/Cs))xc2x7Vccs/2. 
Thus, read voltage xcex94V is the same in both the H-data and L-data read operations, as given by the following expression:
xcex94V=(1/(1+Cb/Cs))xc2x7Vccs/2. 
Read voltage xcex94V in the H-data read operation is made equal to that in the L-data read operation, to read the H data and L data with the same sense margin at a faster sense timing.
In the conventional DRAM, the memory cell data is read onto one of the bit-lines BL, /BL, and the other bit line is maintained at the precharge voltage. Whether the memory cell data read onto one bit line is H data or L data is determined by comparing the voltage on one bit line with a reference voltage (the precharge voltage on the other bit line).
In memory cell MC (MC0, MC1), a capacitor contact region of the access transistor is an impurity region (source/drain region) formed at the surface of a semiconductor substrate. Accordingly, charges accumulated in storage node SN (SN0, SN1) disappear due to a junction leak current from the impurity region to the substrate region.
More specifically, as shown in FIG. 30, in the case of the H-data storage, storage node SN falls in voltage exponentially with time from the sense power supply voltage Vccs level due to the junction leak current. In the case of the L-data storage, the substrate region is biased to a negative voltage Vbb level, and storage node SN similarly falls in voltage exponentially from ground voltage GND. Accordingly, when the voltage at the storage node storing H-data reaches precharge voltage Vccs/2 at time Tref, whether the memory cell data is at the H level or L level can no longer be determined.
If the voltage at the storage node is further lowered from the precharge voltage Vccs/2 after time Tref, the H data is determined to be L data, resulting in misreading of the data. Therefore, a so-called refresh operation of reading and re-writing the memory cell data must be performed in order to restore the reduced H-data voltage to the original sense power supply voltage Vccs. In the case of the voltage change as shown in FIG. 30, the refresh operation must be performed at time intervals shorter than period Tref.
In miniaturizing DRAM elements, various parameters are proportionally reduced according to the scaling rules. According to the scaling rules, as a DRAM memory cell is miniaturized, impurity concentration of the source/drain region of the access transistor is increased in order to reduce the junction depth. Therefore, impurity concentration of the capacitor contact region of the access transistor is increased, and the junction leak current is increased accordingly (since the difference in impurity concentration between the substrate region and the source/drain region is increased), whereby time period Tref is shortened. Accordingly, the refresh operation must be performed frequently at shorter time intervals. In the normal operation mode, access to the DRAM is not allowed during such a refresh operation. Therefore, a processor is kept in a waiting state, resulting in reduced processing efficiency.
Moreover, in order to sense the L data, N-channel MOS transistors NQ1 and NQ2 in the sense amplifier 900 as shown in FIG. 27 must be turned ON under the condition that their gate-source voltages are lower than Vccs/2. Therefore, N-channel MOS transistors NQ1 and NQ2 must have a threshold voltage lower than the bit-line precharge voltage. Similarly, in order to sense the H data, P-channel MOS transistors PQ1 and PQ2 must be rendered conductive under the condition that their gate-source voltages are lower than intermediate voltage Vccs/2. However, if the absolute value of threshold voltage of an MOS transistor is reduced, a sub-threshold current (off-leak current) is increased.
FIG. 31 is a diagram showing a voltage at each node of sense amplifier 900 after the sensing operation is completed. In FIG. 31, bit lines BL and /BL are respectively driven to sense power supply voltage Vccs and ground voltage GND. In this state, the gate of MOS transistor PQ1 is at the ground voltage level, but the source and drain thereof are both at the sense power supply voltage Vccs level. Therefore, no current flows through MOS transistor PQ1. However, the gate and source of MOS transistor PQ2 are both at the sense power supply voltage Vccs, and the drain thereof is at the ground voltage GND level. In this case, an off-leak current Ioff1 flows from internal power supply node 900a into bit line /BL through MOS transistor PQ2. The leak current further flows through MOS transistor NQ2 into second internal power source node 900b. 
The gate and source of MOS transistor NQ1 are both at the ground voltage GND, but bit line BL is at the sense power supply voltage Vccs level. Therefore, due to the current from bit line BL and P-channel MOS transistor PQ1, an off-leak current Ioff2 flows through MOS transistor NQ1.
Off-leak currents Ioff1 and Ioff2 increase as the absolute value of a threshold voltage is reduced. In other words, a leak current Icc3 flowing in a so-called active standby state after the sensing operation is completed is increased. Particularly, in the case of a multi-bank structure, this leak current is increased when a plurality of sense amplifier bands are all in the active standby state. Thus, in the case where an array power supply voltage, i.e., an operating power supply voltage of the sense amplifier circuitry, is to be set to 1.5 V or less, for example, a threshold voltage of the sense amplifier transistors must be reduced to as low as 0.4 V or less. As a result, the active standby current (Icc3) is disadvantageously increased.
It is an object of the present invention to provide a semiconductor memory device capable of being driven with a low voltage and having long refresh intervals.
It is another object of the present invention to provide a semiconductor memory device having low current consumption and improved access efficiency.
A semiconductor memory device according to one aspect of the invention includes a plurality of unit cells arranged in a matrix rows and columns. Each of the plurality of unit cells includes first and second storage elements each including a transistor and a capacitor.
The semiconductor memory device according to the one aspect of the invention further includes a plurality of bit line pairs provided corresponding to respective columns, and each connecting to the unit cells of a corresponding column. Each of the bit line pairs includes first and second bit lines respectively coupled to the first and second storage elements of the unit cells of a corresponding column.
The semiconductor memory device according to the one aspect of the invention further includes a plurality of row selection lines provided corresponding to respective rows, and each connecting to the unit cells of a corresponding row. Each of the row selection lines includes a first word line to which the first storage elements of the unit cells of a corresponding row are connected, and a second word line to which the second storage elements of the unit cells of the corresponding row are connected.
The semiconductor memory device according to the one aspect of the invention further includes a row selection circuit for driving both the first and second word lines of a row selection line corresponding to an addressed row into a selected state according to an address signal, and a bit-line voltage setting circuit for setting the voltage on the first and second bit lines of each bit line pair to a voltage level different from a predetermined voltage in a standby state, the predetermined voltage being equal to half a sum of voltages respectively corresponding to high-level and low-level data stored in the first and second storage elements.
A semiconductor memory device according to another aspect of the invention includes a plurality of unit cells arranged in a matrix of rows and columns. Each of the plurality of unit cells has first and second storage elements. The first storage element includes first and third transistors, and a first capacitor connected to the first and third transistors. The second storage element includes second and fourth transistors, and a second capacitor connected to the second and fourth transistors.
The semiconductor memory device according to the another aspect of the invention further includes a plurality of first-port bit line pairs provided corresponding to respective columns and each having the unit cells of a corresponding column connected thereto, and a plurality of second-port bit line pairs provided corresponding to the respective columns and each having the unit cells of a corresponding column connected thereto. Each of the first-port bit line pairs includes a first first-port bit line coupled to the first transistor, and a second first-port bit line coupled to the second transistor. Each of the second-port bit line pairs includes a first second-port bit line coupled to the third transistor, and a second second-port bit line coupled to the fourth transistor.
The semiconductor memory device according to the another aspect of the invention further includes: a plurality of first-port word lines provided corresponding to respective rows, and each connecting to the first and second transistors of the unit cells of a corresponding row; a plurality of second-port word lines provided corresponding to the respective rows, and each connecting to the third and fourth transistors of the unit cells of a corresponding row; a first-port bit-line voltage setting circuit provided corresponding to each of the first-port bit line pairs for setting a respective voltage on the first and second first-port bit lines of each first-port bit-line pair to a voltage level different from a predetermined voltage level when the first-port word lines are in a non-selected state, the predetermined voltage level being equal to half a sum of voltages respectively corresponding to high-level and low-level data stored in the first and second storage elements; and a second-port bit-line voltage setting circuit for setting a respective voltage on the first and second second-port bit lines of each second-port bit line pair to a voltage level different from the predetermined voltage level when the second-port word lines are in the non-selected state.
A semiconductor memory device according to still another aspect of the invention includes a plurality of first bit lines extending in a column direction, and a plurality of second bit lines extending in the column direction alternately with the plurality of first bit lines. The first and second bit lines are provided so that the adjacent first and second bit lines make a bit-line set.
The semiconductor memory device according to the still another aspect of the invention further includes an active region extending in the column direction under the first and second bit lines of each set in alignment with the first and second bit lines of a corresponding set as viewed two-dimensionally. These active regions are regions for forming transistors, and the adjacent active regions in the row direction are isolated from each other by a corresponding insulating region.
The semiconductor memory device according to the still another aspect of the invention further includes a plurality of first word lines extending in the row direction, and a plurality of second word lines extending in the row direction. The plurality of second word lines are arranged alternately with the plurality of first word lines, and the adjacent first and second word lines make a word-line set.
The semiconductor memory device according to the still another aspect of the invention further includes a capacitor provided between the first and second word lines of each set. These capacitors are aligned in the row and column directions.
The semiconductor memory device according to the still another aspect of the invention further includes a plurality of first bit-line contacts provided for first bit lines so as to align in the row direction, each for making an electrical contact between a corresponding first bit line and a corresponding active region, and a plurality of second bit-line contacts provided for second bit lines so as to align in the row direction, each for making a contact between a corresponding second bit line and a corresponding active region. The second bit-line contacts are provided corresponding to the first bit-line contacts so that each second bit-line contact is located opposite to a corresponding first bit-line contact with respect to a corresponding capacitor contact for making a contact between a corresponding capacitor and a corresponding active region. The first and second bit-line contacts are arranged sandwiching a set of the first and second word lines. Moreover, the first and second bit-line contacts are located at prescribed intervals along the column direction.
By reading the memory cell data onto a bit line pair, the voltage difference between the bit line pair becomes twice that in the conventional structure. Therefore, a sufficiently long refresh interval can be obtained.
Moreover, by setting the bit lines to the voltage level of the data, the sensing transistors in the sense amplifier circuitry can be turned ON as soon as the bit line voltage is shifted by the threshold voltage of the sensing transistors from the data voltage level. Accordingly, the threshold voltage of the transistor in the sense amplifier circuitry can be increased, and the sense power supply voltage can be reduced. As a result, a semiconductor memory device driven with a low voltage and having a low current consumption can be implemented.
Moreover, the active regions extend in the same direction as that of the bit lines, and the active regions are isolated from each other in the row direction by an isolating region. The first-port and second-port bit-line contacts are alternately arranged along the column direction so as to be opposite to each other with respect to a corresponding capacitor contact in each set. Accordingly, the memory cells forming the first and second storage elements are arranged efficiently, whereby four-transistor/two-capacitor memory cells can be formed with a small occupying area. Moreover, the layout pattern is made regular in the row and column direction, whereby accurate patterning is assured.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.